1. Field of the Invention
The present invention relates to an insulated gate thin film transistor formed on an insulating material (e.g., glass) or a material such as a silicon wafer having thereon an insulating film (e.g., silicon oxide), and to a method for fabricating the same. The present invention is particularly effective for thin film transistors fabricated on a glass substrate having a glass transition temperature (deformation temperature or deformation point) of 750xc2x0 C. or less. The thin film transistor according to the present invention is useful for driver circuits of, for example, active matrix liquid crystal displays and image sensors, as well as for three dimensional integrated circuits.
2. Description of the Related Art
Thin film transistors (referred to simply hereinafter as xe2x80x9cTFTsxe2x80x9d) are widely employed for driving, for example liquid crystal displays of active matrix type and image sensors. TFTs of crystalline silicon having a higher electric field mobility are also developed as an alternative for amorphous silicon TFTs to obtain high speed operation. However, TFTs with further improved device characteristics and durability can be obtained by forming an impurity region having a high resistance (high resistance drain; HRD).
FIG. 4A shows a cross section view of a conventional TFT having an HRD. The active layer comprises low resistance regions 1 and 5, a channel forming region 3, and high resistance regions 2 and 4 formed therebetween. A gate insulating film 6 is provided to cover the active layer, and a gate electrode 7 is formed on the channel forming region 3 through the gate insulating film 6. An interlayer dielectric 8 is formed to cover the gate electrode 7, and source/drain electrodes 9 and 10 are connected to the low resistance regions 1 and 5. At least one of the elements selected from oxygen, nitrogen, and carbon is introduced into the high resistance regions 2 and 4.
The introduction of at least one of the elements above, however, requires the use of photolithography. Thus, it is difficult to form high resistance regions on the edge portion of the gate electrode in a self-alignment; hence, the TFTs are fabricated at a low yield, and moreover, the TFTs thus obtained are not uniform in quality.
The present invention provides TFTs having uniform device characteristics at a high yield by forming the high resistance regions in a self-alignment without using photolithography.
A TFT according to the present invention is shown schematically in FIG. 4B. The position and the size of high resistance (impurity) regions 12 and 14 depend on a gate insulating film 15 and a gate electrode portion (comprising a gate electrode 17 and in some cases, an anodic oxide film 17xe2x80x2). That is, at least one of nitrogen, oxygen, carbon, etc., is introduced into the active layer using the gate electrode portion and the gate insulating film 16 as masks. By controlling the accelerating voltage of the ions to control the depth of ion doping, the ion concentration is found to be maximum at a predetermined depth. In case nitrogen ions are introduced at an accelerating voltage of 80 kV, a maximum concentration for nitrogen ions can be achieved at a depth of 1,000 xc3x85. Even in an active layer, the concentration of nitrogen ions differs with the depth in such a case.
In case a gate insulating film and a gate electrode portion are provided at a thickness of 1,000 xc3x85 and 3,000 xc3x85 or more, respectively, the gate electrode portion is sufficiently thick to prevent nitrogen ions from introducing into the active layer formed under the gate electrode portion. As illustrated in FIG. 4C, most of the nitrogen ions pass through the active layer 21 at a portion (shown with line Bxe2x80x94Bxe2x80x2) where the active layer is exposed. Accordingly, nitrogen ions are found at a highest concentration at a portion under the active layer 21, e.g., the substrate. In contrast to this, a highest nitrogen ion concentration is achieved in the active layer at a portion (line Axe2x80x94Axe2x80x2) where the gate electrode portion is not present and the gate insulating film 16 is present.
Accordingly, a high resistance region can formed in a self-alignment by selectively introducing the nitrogen ions into the active layer under the portion at which the gate insulating film is present and the gate electrode portion is not present. Referring to FIG. 4D, low resistance (impurity) regions 11 and 15 and high resistance regions 12 and 14 are formed by doping an N- or P-type impurity. The N- or P-type impurity can be doped before introducing nitrogen ions.
In case of forming an anodic oxide 17xe2x80x2 on the surface of the gate electrode 17, the high resistance regions 12 and 14 are offset from the gate electrode 17. The displacement x according to the offset depends on the chickens of the anodic oxide 17xe2x80x2, and the low resistance regions 11 and 15 are displaced horizontally form the gate electrodes 17 for a distance corresponding to the sum of the width of the region 12 and the displacement x.
According to the present invention, an oxide layer formed by anodically oxidizing the gate electrode and the like is used as the gate insulating film 16 to form the high resistance regions in a self-alignment. The thickness of the anodic oxide can be precisely controlled. More specifically, the anodic oxide film can be formed uniformly at a thickness of 1,000 xc3x85 or less to a thickness of 5,000 xc3x85 or more (e.g., to 1 xcexcm). Thus, this is preferred because a high resistance region can be formed with a greater degree of freedom, and, moreover, in case of using a self-aligned process, the high resistance region can be formed without causing fluctuation in its width.
In contrast to a so-called barrier type anodic oxide which is etched only by a hydrofluoric etchant, a porous type anodic oxide can be selectively etched by a phosphoric acid etchant and the like. Accordingly, an etching treatment can be affected without damaging other materials constituting the TFT, for example, silicon and silicon oxide. In case of dry etching, the barrier or porous anodic oxide is extremely resistant against etching, and exhibits a sufficiently high selectivity ratio in case of etching with respect to silicon oxide.
According to the present invention, a TFT can be fabricated by the following processes. Thus, high resistance regions can be formed with a higher certainty and therefore mass production is improved.
Referring to FIGS. 1A to 1E, a basic process for fabricating a TFT according to the present invention is described below. A base insulating film 102 is formed on a substrate 101. An active layer 103 is formed from a crystalline semiconductor (a semiconductor comprising a crystal even at a small quantity, for example, a single crystal semiconductor, polycrystalline semiconductor, semi-amorphous semiconductor or the like is referred to as xe2x80x9ca crystalline semiconductorxe2x80x9d in the present invention. An insulating film 104 comprising silicon oxide is formed to cover an active layer 103, and a coating is formed by an anodically oxidizable material. Preferably, an anodically oxidizable material such as aluminum, tantalum, titanium, and silicon, is used as the coating material. Moreover, a monolayered gate electrode using one of the above materials as well as a multilayered gate electrode comprising two layers or more of the above materials can be utilized. As shown in FIG. 9, for example, a double layered structure comprising titanium silicide 901 formed on aluminum 902 or a double layered structure comprising aluminum 901 formed on titanium nitride 902 can be used. Each of the layers is provided at a thickness depending on the device characteristics.
A mask film used as the mask in the anodic oxidation is formed to cover the coating and then the coating and the mask film are patterned and etched simultaneously, thereby to form a gate electrode 105 and a mask film 106. The mask film can be formed using a photoresist used in an ordinary photolithography process, a photosensitive polyimide, or a general etchable polyimide. (FIG. 1A).
A porous anodic oxide 107 is formed on both sides of the gate electrode 105 by applying an electric current to the gate electrode 105 in the electrolytic solution. The anodic oxidation is effected using an aqueous acidic solution containing from 3 to 20% of citric acid, nitric acid, phosphoric acid, chromic acid, sulfuric acid, and the like. An anodic oxide form 0.3 to 25 xcexcm in thickness, more specifically, 0.5 xcexcm in thickness, is formed by applying a voltage of about 10 to 30 V. The mask film 105 is removed by etching after the anodic oxidation. (FIG. 13)
A barrier anodic oxide 108 can be formed on both sides and the upper surface of the gate electrode 105 by applying a current thereto in an ethylene glycol solution containing from 3 to 10% of tartaric acid, boric acid, or nitric acid. The thickness of the anodic oxide thus formed depend on the voltage applied between the gate electrode 105 and the electrode face thereto.
The barrier anodic oxide is formed after forming the porous anodic oxide. The barrier anodic oxide 108 is formed not on the outer side of the porous anodic oxide 107, but between the porous anodic oxide 107 and the gate electrode 105. The etching rate of a phosphoric acid etchant to a porous anodic oxide is 10 times or more higher with respect to that to a barrier anodic oxide. Accordingly, the gate electrode 105 is protected from a phosphoric acid etchant because the barrier anodic oxide 108 remains substantially unetched in a phosphoric acid etchant (FIG. 1C).
The insulating film 104 is etched by dry etching, wet etching or the like. The etching can be effected until the active layer is exposed, or it may be stopped in the intermediate state. Preferably from the viewpoint of mass production, yield, and the uniformity of the film, the insulating film is completely etched until the active layer is exposed. The thickness of the gate insulating film covered by the anodic oxide 107 and the gate electrode 105 remains unchanged during the etching. In case dry etching using a fluorine-based gas (e.g., NF3 or SF6) is effected on a gate electrode 105 containing mainly aluminum, tantalum, and titanium as well on an insulating film 104 containing mainly silicon oxide, the insulating film 104 made of a silicon oxide can be etched rapidly. Since the etching rate is sufficiently low for aluminum oxide, tantalum oxide, and titanium oxide, the insulating film 104 can be etched selectively. The insulating film 104 can be etched rapidly and selectively by wet etching using a hydrofluoric acid based etchant such as hydrofluoric acid diluted to 1/100 (FIG. 1D).
The anodic oxide 107 is removed thereafter. A phosphoric acid based aqueous solution, such as a mixed acid of phosphoric acid, acetic acid, and nitric acid, is preferred as the etchant.
Thus, a part of the insulating film 104 (referred to hereinafter as xe2x80x9cgate insulating filmxe2x80x9d) can be remained. A gate insulating film 104xe2x80x2 is present under the gate electrode 105 and the barrier anodic oxide 108, as well as under the porous anodic oxide 107 to a position extended for a distance y from the edge portion of the barrier anodic oxide 108. The distance y is determined in a self-alignment. Accordingly, a region of the active layer 103 on which the gate insulating film 104xe2x80x2 is formed and a region on which the gate insulating film 104xe2x80x2 is not formed are for med in a self-alignment. A high resistance region containing the ions at a high concentration is formed in a self-alignment with respect to the gate electrode by introducing ions such as nitrogen, oxygen, and carbon into the active layer.
The distance x between the edge portion of the gate electrode and the edge portion of the source or the drain region (see FIG. 4D) corresponds to the offset width, and the width of the high resistance region is controlled in a self-alignment by the distance y. Referring to FIGS. 1D and 2C, the edge portion 109 of the gate insulating film 104xe2x80x2 coincides approximately with the edge portion 121 of the high resistance portion 112. The high resistance region in a conventional technology is formed in a non-self-alignment. Accordingly, it is difficult to form the high resistance region and the gate electrode at the same position for all the TFTs on the same substrate. In the present invention, however, the width of the anodic oxide 107 can be precisely controlled by the applied current (charge) for anodic oxide.
The offset width between the gate electrode and the high resistance region can be set arbitrary by controlling the thickness of the anodic oxide 108. In general, the ON/OFF ratio increases as the reverse leak current reduces in an offset state. Thus, the TFT according to the present invention is suitable for a pixel TFT for controlling the pixels of an active matrix liquid crystal display in which a low leak current is required. However, since the hot carriers generated at the edge portions of the high resistance region are trapped by the anodic oxide, the characteristics of the TFT deteriorate.
In case of a TFT having a small offset, the deterioration of the TFT characteristics due to the trapping of hot carriers reduces and the ON current increases, but the leak current reversely increases. Accordingly, a TFT having a small offset is suitable for a TFT in which a large current drive capacity is required, for example, a driver TFT utilized in the peripheral circuits of monolithic active matrices. In practice, the TFT offset is determined by the usage of the TFT.